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communication semiconductors CMX989 data bulletin cdpd mac and data pump processor 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. advance information features applications ? reed-solomon encoder, decoder and error correction ? mac and physical layer functions: minimize host controller burden and power ? tx and rx byte-wide cdpd frame fifos ? encapsulates/de-encapsulates cdpd frames to/from over-air baseband signals ? parallel bus hardware interface to host cpu ? 2.7v to 5.5v supply, 28-pin tssop package ? cdpd (cellular digital packet data) terminals ? pcmcia/pc-card wireless modem modules ? wireless internet terminals ? portable and mobile wireless data terminals ? line power/battery applications ? 19.2kbps (bt = 0.5) full duplex gmsk data modems the highly integrated CMX989 cdpd mac and data pump processor integrates complex cdpd mac and physical layer functions to serve as a core engine for high performance, low power cdpd terminal designs. mac layer functions decouple the host cpu from the cdpd airlink to simplify and reduce cdpd protocol stack programming, free cpu capacity for applications, eliminate interface components, and allow cpu sleep time for power savings. physical layer functions mate mac layer to baseband radio signals with minimal host involvement. mac and physical layer functions are intelligently coupled to meet airlink timing requirements. for example: tx emissions automatically start in synchronization with forward channel busy/idle status. the rx cdpd frame fifo is automatically managed to wait for valid synchronization to occur when first started and after lost signal recovery. the radio interface supports simple, low cost, vco-based rf modulators and discriminator-based receivers. independent, programmable gain tx outputs are provided for software trimming and balancing of modulating signals. the host cpu interface is fifo based and organized in cdpd frames, to provide a simple programming interface with low service latency requirements. over-the-air frames are automatically encapsulated and de- encapsulated and include complete reed-solomon encoding, decoding and error correction, color code insertion and related functions. device status bits are accessible and may be individually configured to interrupt the host via the parallel hardware interface. the CMX989 operates from a 2.7v to 5.5v supply over - 40 to 85c and comes in a 28-pin tssop package (CMX989e1)
cdpd mac and data pump processor page 2 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. contents section page 1. block diagram ............................................................................................................... 3 2. signal list .................................................................................................................... .. 4 3. external components ................................................................................................... 5 4. general description ...................................................................................................... 6 4.1 principles of operation....................................................................................................... 6 4.2 detailed function list ........................................................................................................ 7 4.2.1 separate 141-byte tx and rx data buffers, organized as byte-wide cdpd frame fifos ..... 7 4.2.2 encapsulates/de-encapsulates cdpd frames to/from over-air signal systems ..................... 7 4.2.3 19.2kbps (bt = 0.5) gmsk modem data pump ..................................................................... 8 4.3 software description.......................................................................................................... 9 4.3.1 write only registers ........................................................................................................... .... 9 4.3.2 read only registers ............................................................................................................ ... 9 4.3.3 write only register description............................................................................................ 10 4.3.4 read only register description............................................................................................ 14 5. application notes........................................................................................................ 18 5.1 operation sequence........................................................................................................ 18 5.1.1 power up ....................................................................................................................... ....... 18 5.1.2 acquisition of a cdpd channel............................................................................................. 18 5.1.3 receive ........................................................................................................................ ......... 18 5.1.4 transmit ....................................................................................................................... ......... 19 6. performance specification......................................................................................... 20 6.1 electrical performance..................................................................................................... 20 6.1.1 absolute maximum ratings .................................................................................................. 20 6.1.2 operating limits............................................................................................................... ..... 20 6.1.3 operating characteristics ..................................................................................................... 2 1 6.1.4 timing diagrams................................................................................................................ ... 22 6.2 packaging...................................................................................................................... .. 24 note: this product is in development: changes and additions will be made to this specification. items marked tbd or left blank will be included in later issues. information in this data sheet should not be relied upon for final product design. mx-com, inc. reserves the right to change specifications at any time and without notice.
cdpd mac and data pump processor page 3 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 1. block diagram figure 1: block diagram
cdpd mac and data pump processor page 4 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 2. signal list package e1 signal description pin no. name type 1 xtaln o/p the output of the on-chip oscillator 2 xtal/clock i/p the input to the on-chip oscillator, for external xtal circuit or clock 3 irqn a ?wire-orable? output for connection to the host controller's interrupt request input. this output has a low impedance pull down to v ss when active and is high impedance when inactive. 4 d7 bi 5 d6 bi 6 d5 bi 7 d4 bi 8 d3 bi 9 d2 bi 10 d1 bi 11 d0 bi 8-bit bi-directional 3-state controller interface data lines 12 rdn i/p read. an active low logic level input used to control the reading of data from the device into the host controller. 13 wrn i/p write. an active low logic level input used to control the writing of data into the device from the host controller. 14 v ss power the negative supply rail (ground). 15 doc 2 o/p 16 doc 1 o/p connections to the rx level measurement. circuitry. a capacitor should be connected from each pin to v ss . 17 v bias o/p a bias line for the internal circuitry, held at ? v dd . this pin must be decoupled to v ss by a capacitor mounted close to the device pins. 18 rxfb o/p the output of the rx input amplifier and the input to the rx filter. 19 rxin i/p the input to the rx input amplifier. 20 n/c no internal connection, do not use. 21 txop2 o/p 22 txop1 o/p two-point modulator signal output from the device. txop2 is in- phase with txop1. 23 txrfen o/p tx rf enable. control line to enable an external rf power amplifier stage. this signal is also available via the parallel controller interface. 24 a2 i/p 25 a1 i/p 26 a0 i/p three logic level register select inputs. 27 csn i/p chip select. an active low logic level input to the device, used to enable a data read or write operation. 28 v dd power the positive supply rail. levels and voltages are dependent upon this supply. this pin should be decoupled to v ss by a capacitor. notes: i/p = input o/p = output bi = bidirectional 3-state input/output nc = no connection
cdpd mac and data pump processor page 5 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 3. external components figure 2: recommended external components 3.1 typical values: r1 1m ? 5% c3 33pf 20% r2 note 1 10% c4 0.1f 20% r3 100k ? 10% c5 100pf 20% r4 100k ? 10% c6 6.8nf 20% x1 4.9152 mhz (ref. section 6.1) c7 6.8nf 20% c1 0.1f 20% c8 0.1f 20% c2 33pf 20% notes: 1. r2, r3, c4 and c5 form the gain components for the rx input. r2 should be chosen as required by the signal input level, using the following formula: gain = -r3/r2 2. connections labeled ?n/c?: no internal connection, do not use. to achieve good noise performance it is very important to decouple v dd and v bias and to protect the receive path from extraneous in-band signals. it is recommended that the printed circuit board is laid out with a ground plane in the CMX989 area to provide a low impedance connection between the v ss pin and the v dd and v bias decoupling capacitors. it is also important to provide a low impedance connection between the xtal capacitors (c1 and c2) and the ground plane.
cdpd mac and data pump processor page 6 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4. general description this device performs the data encapsulation and synchronization functions of the medium access control (mac) layer part of the cdpd specification, as well as the generation of baseband signals in the physical layer, all of which are specifically for the mobile end station (m-es). for details of the system requirements and telegram formats, the user is referred to ?cellular digital packet data system specification? (release 1.1), volumes 1 to 5, currently available from: cdpd industry input coordinator cellular digital packet data system specification 650 town center drive, suite 820 costa mesa, ca 92626 united states of america 4.1 principles of operation the CMX989 functions (as shown in the block diagram of figure 1) may be accessed and/or controlled via memory mapped 8-bit registers connected to the host controller parallel bus interface. write registers allow the device to be set up, controlled and used for transmission of data. read registers allow received data to be read and the status of the CMX989 to be monitored. there are several registers which can be used to assist end-product manufacture and test and related system test. it is assumed that many applications will be assisted by the use of interrupt routines, so various functions within the device will cause a hardware interrupt, e.g.: when received data is available to be read or space is available to write data for transmission. each hardware interrupt source may be individually disabled (masked) or enabled. the interrupt pin (irqn) is reset high by a read of either irq flags or irq flags 2 registers and the bits read from these registers and the status register reflect the status of the CMX989 at the time the read is performed. the irq flags, irq flags2 and status registers can be polled (without the use of a hardware interrupt routine call) if this is preferred. for reference, the structures of the reverse and forward channel transmissions are shown in figure 3 and figure 4. figure 3: reverse channel transmission structure
cdpd mac and data pump processor page 7 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. figure 4: forward channel transmission structure 4.2 detailed function list 4.2.1 separate 141-byte tx and rx data buffers, organized as byte-wide cdpd frame fifos ? large enough to hold an entire maximum length (136-byte) cdpd frame ? decouples host cpu and cdpd airlink to provide opportunities for cpu powersave and relaxed service routine timing requirements ? rx management automatically flushes erroneous frames and resynchronizes rx buffer on valid frame synchronization ? empty/full status ? tx frames are written byte-by-byte style and separated from subsequent frames by writing to an end of frame marker ? rx frames are read byte-by-byte with each frame boundary indicated by an irq and related status ? read and write status/irq handshake paces each byte transferred to and from fifos 4.2.2 encapsulates/de-encapsulates cdpd frames to/from over-air signal systems ? completed reed-solomon block encode and decode with automated ?fill? function for partially filled tx blocks ? color code automatically extracted from rx stream and inserted into tx stream ? pseudo-random number scrambling ? status flags available for reading or to irq on: number of errors corrected in rx reed-solomon block, number errors in forward sync word, rx busy/idle, rx color code, mdbs decode, etc.
cdpd mac and data pump processor page 8 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.2.3 19.2kbps (bt = 0.5) gmsk modem data pump ? discriminator rx interface ? rx frame synchronization recognizer triggers internal ?upper layer? processing ? intelligent tx emission triggering: ? tx emission start is synchronized to rx busy/idle flag timing ? tx fifo may be loaded before issuing an emission request or emission request may be issued first and remains pending until tx fifo is loaded with enough data to generate a reed-solomon block ? host controller and txrfen signals available to enable ramp-up and ramp-down control of external rf power amplifier stage ? dual, independent gain controlled tx outputs for low frequency response transmit vco architecture
cdpd mac and data pump processor page 9 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.3 software description 4.3.1 write only registers register address register name function a2 a1 a0 write to modem bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 tx data buffer bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 tx color code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 0 tx control 0 0 0 force color code endseq endfrm start enabtx 0 1 1 rx control reset 0 0 zero power enabrx sync error limit 1 0 0 rx modem control 0 0 levres aqlev aqbc pllbw 1 0 1 tx modem control mod 2 gain mod 1 gain 1 1 0 irq mask syncm decm idlem txm colorm errm rxm rxfrmm 1 1 1 irq mask 2 blkrdym 0 rxdebug txwithnorx txrfm rxpulse rx bit 1 rx bit 0 4.3.2 read only registers register address register name function a2 a1 a0 read from modem bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 rx data buffer bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 rx color code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 0 status sync dec idle 0 txrfen err 0 0 0 1 1 irq flags syncf decf idlef txf colorf errf rxf rxfrmf 1 0 0 rx error data corrected errors over8 sync errors 1 0 1 irq flags 2 blkrdyf env eopn 0 txrff 0 0 0 1 1 0 *** reserved *** 0 0 0 0 0 0 0 0 0 1 1 *** reserved *** 0 0 0 0 0 0 0 0
cdpd mac and data pump processor page 10 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.3.3 write only register description 4.3.3.1 tx data buffer register (hex address $00) this is a write only register of the tx data buffer. it should be written in response to a txf irq flag being set to ?1?. bit 7 is the msb. the interval between txf interrupts varies from approximately 16s to 22ms, depending on the position within the internal data processing sequence. 4.3.3.2 tx color code register (hex address $01) this is a write only register of the tx color code. this value for the tx color code is used when the force color code (bit 4 of the tx control register) bit is set to ?1?. bit 7 is the msb. 4.3.3.3 tx control register (hex address $02) (bits 7,6 and 5) unused, set to ?0? force color code (bit 4) when this bit is ?1? the color code transmitted in the first block of the reverse channel will be the byte defined in the tx color code register. when this bit is ?0? the color code transmitted will be the color code byte previously received on the forward channel and recorded in the rx color code read-only register. endseq (bit 3) write a ?1? to this bit when the last byte of the last frame in the sequence has loaded. endfrm (bit 2) at the end of every frame (2-136 bytes) write a ?1? to this bit. start (bit 1) write a ?1? to this bit to start the transmission on the reverse channel at the next available slot. enabtx (bit 0) when this bit is ?1? the tx (reverse channel) is enabled. when this bit is ?0? the tx (reverse channel) is disabled and enters a powersave condition. in this condition the txop1 and txop2 outputs are at v bias . 4.3.3.4 rx control register (hex address $03) reset (bit 7) write a ?1? followed by a ?0? to this bit just after power up to initialize the device into a zero-power and ?safe? condition. (bits 6 and 5) unused, set to ?0?. zero power (bit 4) when this bit is set to ?0? the whole device is disabled and set to minimum power including the crystal oscillator. allow 20ms for the crystal oscillator to stabilize when coming out of this zero-power state. enabrx (bit 3) when this bit is ?1? the rx (forward channel) is enabled. when this bit is ?0? the rx (forward channel) is disabled and enters a powersave condition. sync error limit (bits 2, 1 and 0) this 3-bit number specifies the greatest number of bits that can be in error in the synchronization word. bit 2 is the msb. if the synchronization word is recognized with less than or equal to this number of errors, the syncf bit is set to ?1? and the actual number of errors is loaded into sync errors (bits 2, 1 and 0 of the rx error data register). the rxdata in that block is then processed.
cdpd mac and data pump processor page 11 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.3.3.5 rx modem control (hex address $04) this register is for test purposes only and should be set to all ?0s? for normal operation. (bits 7 and 6) unused, set to ?0? levres (bits 5 and 4) these two bits set the response time of the rx signal amplitude and dc offset measuring circuits according to the table below: b5 b4 setting action 0 0 peak averaging track input signal using bit peak averaging 0 1 peak detect track input signal using peak detect 1 0 lossy peak detect track input signal using lossy peak detection 1 1 hold keep current values of amplitude and offset this setting will be temporarily overridden by the automatic sequencing of an aqlev command. aqlev (bit 3) whenever the aqlev bit is set to ?1? it initiates an automatic sequence designed to measure the amplitude and dc offset of the received signal as rapidly as possible. this sequence involves setting the measurement circuits to respond quickly at first, then gradually increasing their response time, hence improving the measurement accuracy, until the ?normal? value set by the levres bits is reached. setting this bit to ?0? (or changing it from ?1? to ?0?) has no effect. aqbc (bit 2) whenever the aqbc bit is set to ?1? it initiates an automatic sequence designed to achieve bit timing synchronization with the received signal as quickly as possible. this involves setting the phase locked loop of the received bit timing extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing synchronization is achieved, until it reaches the ?normal? value set by the pllbw bits. setting this bit to ?0? (or changing it from ?1? to ?0?) has not effect. pllbw (bits 1 and 0) these two bits set the bandwidth of the rx clock extraction pll circuit according to the table below: b1 b0 pll bandwidth suggested use 0 0 medium wide tolerance xtals or long preamble acquisition 0 1 wide quick acquisition 1 0 narrow 20ppm or better xtals 1 1 hold signal fades this setting will be temporarily overridden by the automatic sequencing of an aqbc command.
cdpd mac and data pump processor page 12 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.3.3.6 tx modem control register (hex address $05) mod 2 gain (bits 7, 6, 5 and 4) these bits control the amplitude of the txop2 output according to the table below. (bit 7) (bit 6) (bit 5) (bit 4) gain (db) 0 0 0 0 off (o/p at vbias) 0 0 0 1 -5.6 0 0 1 0 -5.2 0 0 1 1 -4.8 0 1 0 0 -4.4 0 1 0 1 -4.0 0 1 1 0 -3.6 0 1 1 1 -3.2 1 0 0 0 -2.8 1 0 0 1 -2.4 1 0 1 0 -2.0 1 0 1 1 -1.6 1 1 0 0 -1.2 1 1 0 1 -0.8 1 1 1 0 -0.4 1 1 1 1 0.0 mod 1 gain (bits 3, 2, 1 and 0) these bits control the amplitude of the txop1 output according to the table below. (bit 3) (bit 2) (bit 1) (bit 0) gain (db) 0 0 0 0 off (o/p at v bias ) 0 0 0 1 -5.6 0 0 1 0 -5.2 0 0 1 1 -4.8 0 1 0 0 -4.4 0 1 0 1 -4.0 0 1 1 0 -3.6 0 1 1 1 -3.2 1 0 0 0 -2.8 1 0 0 1 -2.4 1 0 1 0 -2.0 1 0 1 1 -1.6 1 1 0 0 -1.2 1 1 0 1 -0.8 1 1 1 0 -0.4 1 1 1 1 0.0
cdpd mac and data pump processor page 13 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.3.3.7 irq mask register (hex address $06) these bits prevent interrupts from occurring as detailed below: syncm (bit 7) when this bit is set to ?1? the sync interrupt will be gated out to the irqn pin. when this bit is set to ?0? the sync interrupt will be inhibited. this bit has no effect on the contents of the status register. decm (bit 6) when this bit is set to ?1? the dec interrupt will be gated out to the irqn pin. when this bit is set to ?0? the dec interrupt will be inhibited. this bit has no effect on the contents of the status register. idlem (bit 5) when this bit is set to ?1? the idle interrupt will be gated out to the irqn pin. when this bit is set to ?0? the idle interrupt will be inhibited. this bit has no effect on the contents of the status register. txm (bit 4) when this bit is set to ?1? the tx interrupt will be gated out to the irqn pin. when this bit is set to ?0? the tx interrupt will be inhibited. this bit has no effect on the contents of the status register. colorm (bit 3) when this bit is set to ?1? the color interrupt will be gated out to the irqn pin. when this bit is set to ?0? the color interrupt will be inhibited. this bit has no effect on the contents of the status register. errm (bit 2) when this bit is set to ?1? the err interrupt will be gated out to the irqn pin. when this bit is set to ?0? the err interrupt will be inhibited. this bit has no effect on the contents of the status register. rxm (bit 1) when this bit is set to ?1? the rx interrupt will be gated out to the irqn pin. when this bit is set to ?0? the rx interrupt will be inhibited. this bit has no effect on the contents of the status register. rxfrmm (bit 0) when this bit is set to ?1? the rxfrm interrupt will be gated out to the irqn pin. when this bit is set to ?0? the rxfrm interrupt will be inhibited. this bit has no effect on the contents of the status register.
cdpd mac and data pump processor page 14 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.3.3.8 irq mask 2 register (hex address $07) this register is the counterpart to irq flags 2 register. apart from txrfm and possibly blkrdym, the bits in this register are mainly for test purposes and should be set to all ?0s? for normal operation. blkrdym (bit 7) when this bit is set to ?1? the blkrdy interrupt will be gated out to the irqn pin. when this bit is set to ?0? the blkrdy interrupt will be inhibited. this bit has no effect on the contents of the status register. (bit 6) unused, set to ?0?. rxdebug (bit 5) when this bit is ?1? the rx (forward channel) will load data every 420 bits, without detecting a sync word. when this bit is ?0? the device operates normally. this bit is normally used for debugging only, but could be used in conjunction with bit error rate measurements. txwithnorx (bit 4) when this bit is ?1? the tx (reverse channel) will transmit without waiting for the rx (forward channel) to synchronize as required by the cdpd specification (release 1.1, part 402, section 5.3.1, figure 402-16). when this bit is ?0? the device operates normally. txrfm (bit 3) when this bit is set to ?1? the txrf interrupt will be gated out to the irqn pin. when this bit is set to ?0? the txrf interrupt will be inhibited. this bit has no effect on the contents of the status register. rxpulse (bit 2) when the two bits ?rx bit 1? and ?rx bit 0? are set appropriately and this bit has ?1? written to it, an internal test sequence will be clocked into the reed-solomon decoder and the receiver will output the bits as required by the cdpd specification (release 1.1, part 402, appendix 402-a, table 402-8). rx bit 1, rx bit 0 (bits 1 and 0) these two bits set the internally generated test sequence for the receiver according to the table below: bit 1 bit 0 function 0 0 normal operation 0 1 test sequence 0 errors 1 0 test sequence 8 errors 1 1 test sequence 9 errors 4.3.4 read only register description 4.3.4.1 rx data buffer register (hex address $00) this is a read-only register of the receive data buffer. it should be read in response to an rxf irq flag being set to ?1?. bit 7 is the msb. the interval between rxf interrupts varies from approximately 16s to 22ms, depending on the position within the internal data processing sequence. 4.3.4.2 rx color code register (hex address $01) this is a ready-only register of the color code on the rx (forward channel). it is updated every time the syncf irq flag is set to ?1?. bit 7 is the msb.
cdpd mac and data pump processor page 15 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.3.4.3 status register (hex address $02) this is a read-only register that contains the status of the various functions on the device as described below: sync (bit 7) this bit is set to ?1? if a forward channel synchronization word has been received successfully. (see sync errors and sync error limit). this bit is reset to ?0? when the sync word has not been detected for more than 420 bits (i.e. sync lost). dec (bit 6) this bit indicates the decode status of the mobile data base station (mdbs) on the forward channel. this bit is set to ?1? when the station fails to decode data successfully, and is reset to ?0? when the station is successful in decoding data. this bit will only change and be valid if sync (bit 7) is set to ?1?. idle (bit 5) this bit indicates the activity of the mobile data base station (mdbs) on the forward channel. this bit is set to ?1? when the station is in an idle state, and reset to ?0? when the station is in a busy state. this bit will only change and be valid if sync (bit 7) is set to ?1?. the value of this bit is not specified if sync (bit 7) is reset to "0". the idle bit is derived from a majority decision on the most recently received group of five consecutive busy/idle bits, as in the cdpd specification (release 1.1, part 402, section 4.5, figure 402-7). the first block of data received in the forward channel will not output any data until the sync word has been found. once this has been found, the majority decision of the most recent group of busy/idle bits will be output in the status register, and the idlef bit will be set to ?1? in the irq flags register. the next six groups of busy/idle bits generate idle bits as they are received and, so long as the sync word remains correct, these successive idle bits are output as the groups of busy/idle bits are received. (bit 4) unused, will be set to ?0?. txrfen (bit 3) this bit is set to "1" approximately two bits (104s) before the dotting sequence leaves txop1 or txop2 outputs and is reset to "0" at the end of transmission from txop1 and txop2. this signal is also available as a direct output on the txrfen pin, where it can be used to enable an external rf power amplifier stage. err (bit 2) this bit indicates whether the data currently being read out from rx data buffer has any errors. if this bit is set to ?1? there are errors that cannot be corrected and the host controller should discard all data in the present frame as that frame cannot be successfully completed. it will then search and re-synchronize to the next frame flag, before making any more data available. when this bit is set to ?0? there are no errors in the block currently being read. note: due to the CMX989's internal buffer, the data currently being read at the CMX989/controller interface may be up to 5 reed-solomon blocks older than the data currently being received at the CMX989/fm demodulator interface. (bits 1 and 0) unused, will be set to ?0?.
cdpd mac and data pump processor page 16 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.3.4.4 irq flags register (hex address $03) this is a read-only register that contains flags to indicate the source of an interrupt, as described below: syncf (bit 7) this bit is set to ?1? when the device has decoded the sync word on the forward channel. it also is set to ?1? if, after detecting sync, it fails to detect it 420 bits later, indicating sync has been lost. the state of the sync can be read from the status register. this bit is reset to ?0? after a ?read? of the irq flags register. when this bit is set to ?1? an interrupt may be generated, depending on the state of the irq mask register. decf (bit 6) this bit is set to ?1? when the decode status of the mobile data base station (mdbs) in the forward channel changes state. the decode state can be read from the status register. this bit is reset to ?0? after a ?read? of the irq flags register. when this bit is set to ?1? an interrupt may be generated depending on the state of the irq mask register. idlef (bit 5) this bit is set to ?1? when the idle status of the mobile data base station (mdbs) in the forward channel changes state. the idle state can be read from the status register. this bit is reset to ?0? after a ?read? of the irq flags register. when this bit is set to ?1? an interrupt may be generated depending on the state of the irq mask register. txf (bit 4) this bit provides handshaking flow control when writing data bytes to the tx (reverse channel) data buffer. it is set to ?1? whenever the buffer is not full and new data can be loaded in to the tx data buffer register. it is reset to ?0? after a ?write? to the tx data buffer register. when this bit is set to ?1? an interrupt may be generated depending on the state of the irq mask register. the interval between txf interrupts varies from approximately 16s to 22ms, depending on the position within the internal data processing sequence. colorf (bit 3) this bit is set to ?1? when a color code is successfully received on the forward channel and placed in the rx color code register. it is reset to ?0? after a read of the irq flags register. when this bit is set to ?1? an interrupt may be generated depending on the state of the irq mask register. errf (bit 2) this bit is set to ?1? when the err status changes. this bit is reset to ?0? after a ?read? of the irq flags register. when this bit is set to ?1? an interrupt may be generated depending on the state of the irq mask register. rxf (bit 1) this bit provides handshaking flow control when reading data bytes from the rx (forward channel) data buffer. it is set to ?1? whenever the buffer is not empty and data is available to be read from the rx data buffer register. it is reset to ?0? after a ?read? of the rx data buffer register. when this bit is set to ?1? an interrupt may be generated depending on the state of the irq mask register. the interval between rxf interrupts varies from approximately 16s to 22ms, depending on the position within the internal data processing sequence. rxfrmf (bit 0) this bit is used when reading the receiver data. it is set to ?1? when the byte about to be read from the receiver data buffer is the first byte of a new frame. it is reset to ?0? after a ?read? of the irq flags register. when this bit is set to ?1? an interrupt may be generated depending on the state of the irq mask register.
cdpd mac and data pump processor page 17 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.3.4.5 rx error data register (hex address $04) this is a read-only register that contains receiver performance data. corrected errors (bits 7, 6, 5 and 4) this 4-bit number indicates the number of reed-solomon symbol errors before error correction that are in the most recently received 63-symbol reed-solomon block. they are updated every time the syncf bit is set in the irq flags register. bit 7 is the msb. over8 (bit 3) this bit is set to "1" if the most recently received reed-solomon block has greater than 8 errors. i.e. the data has too many errors to enable the reed-solomon error correction to work. it is updated every time the syncf bit is set in the irq flags register and is reset to "0" if 8 errors or fewer are encountered. sync errors (bits 2, 1 and 0) this 3-bit number indicates the number of errors in the most recently received synchronization word. it is updated whenever the synchronization word is in error less than or equal to the number specified by the sync error limit bits of the rx control register. it also implies the synchronization word has been received successfully and sets the sync bit to ?1? (see status register above). bit 2 is the msb. note: these bits all refer to the data most recently received at the rx input and are not necessarily the same as previously received and buffered data which is currently being read by the CMX989's host controller. 4.3.4.6 irq flags 2 register (hex address $05) bits 5 and 6 of this register are for test purposes only and their contents should be ignored during normal operation. blkrdyf (bit 7) this is the ?block ready flag? and is set to ?1? when the receiver decodes the currently received reed-solomon block. it is reset to ?0? after a read of the irq flags 2 register. when this bit is set to ?1? an interrupt may be generated depending on the state of the irq mask 2 register. env (bit 6) a circuit monitors the doc voltage levels, which are an indication of the received signal amplitude envelope. if the doc voltages are more than 6% of v dd apart (0.3v when v dd = 5.0v) then this bit will be set to ?1?. it is reset to ?0? when the doc voltages are less than 6% of v dd apart. note: the env output will also be triggered when receiving high levels of noise or other in-band signals. eopn (bit 5) a circuit monitors the receive waveform. if the received signal remains close to the centre of the received data levels (as stored on the doc capacitors) for more than approximately 3 bit-times then this bit will be set to ?1?. if the input signal level goes towards either of the doc capacitor values this bit will be set to ?0?. note: when a data signal is not being received and the doc capacitors have discharged or if there are high levels of noise then the value of the eopn bit will be unreliable and so it should be used in conjunction with the env bit. (bit 4) unused, will be set to ?0?. txrff (bit 3) this bit is set to ?1? when the tx rf enable bit (txrfen) changes state. this bit is reset to ?0? after a ?read? of the irq flags 2 register. when this bit is set to ?1? an interrupt may be generated depending on the state of the irq mask 2 register. (bits 2, 1 and 0) unused, will be set to ?0?.
cdpd mac and data pump processor page 18 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 5. application notes 5.1 operation sequence 5.1.1 power up to initialize the registers to a safe, known state, reset (bit 7 of the rx control register) should be set to ?1?, then set to ?0?, then set to "1", and then to "0" again. this puts the device into the zero-power mode with all functions disabled and resets the device. 5.1.2 acquisition of a cdpd channel the first thing that the device will be required to do is to search for a cdpd forward channel data stream. the sequence below describes how to do this: 1. the likely presence of an rx data stream (cdpd forward channel modulation) may be indicated by the rssi in a process which is separate from, and external to, the CMX989. simultaneously, the CMX989 can search for a cdpd forward channel synchronization word, as follows: 2. write ?1? to zero power and ?1? to enabrx (bits 4 and 3 of the rx control register) to enable the crystal and the receiver. also set the sync error limit (bits 2, 1 and 0 of the rx control register) to a binary value from 0 to 5, depending on the number of errors that can be tolerated in the forward channel synchronization word. 3. write ?1? to syncm (bit 7 of the irq mask register) to enable the detection on interrupt of the forward synchronization word. 4. the device will now interrupt when a cdpd forward channel synchronization word has been detected. an additional local timer could be set to give a timeout after which the host controller could initiate a change of rf channel to search elsewhere for a cdpd forward channel stream. 5. when the interrupt occurs, read the irq flags register to confirm and clear the syncf flag and read the status register to check the sync bit. the syncm bit can be left set to ?1? as further interrupts would indicate that the device has lost the forward synchronization. appropriate action should then be taken. however the user may wish to disable it, as the cdpd reed-solomon decoder has the ability to indicate when the data has lost its integrity. loss of the channel or corruption of the data is indicated by errors in the synchronization word and/or errors in a reed-solomon decoded data block (rx error data register). 6. the rx error data register may also be used in the initial acquisition of the channel as detailed in the cdpd specification (release 1.1, part 402, section 3.2.3). 5.1.3 receive having found a cdpd forward channel stream, the data can be read using the following sequence: 1. write a ?1? to errm, a ?1? to rxm and a ?1? to rxfrmm (bits 2, 1 and 0 of the irq mask register), to enable the rx error irq, the rx data irq and the rx frame flag irq respectively. 2. an rxfrmf interrupt (bit 0 of the irq flags register) indicates that the next byte to be read from the rx data buffer register is the first byte of a new frame. the contents of the rx data buffer register prior to the first rxfrmf interrupt event after enabrx is set to "1" are automatically discarded when the first rxfrmf interrupt occurs. rxf interrupts are also disabled until the first rxfrmf interrupt occurs. 3. using the rxf interrupt (bit 1 of the irq flags register) as a handshake, data can be read from the device. rxf set to "1" indicates that another byte can be read from the rx data buffer register. when rxf remains at "0", the buffer is empty. the frame boundaries are indicated by the rxfrmf interrupt (bit 0 of the irq flags register). note that the host controller should continuously read bytes from the rx data buffer register and then re-assemble the frame within the host controller's memory, rather than wait for a complete frame (indicated by the next rxfrmf interrupt) before starting data transfer. since the frame size is not an integer multiple of the block size, overflow will eventually occur if data is only transferred on frame boundaries. 4. if an errf interrupt (bit 2 of the irq flags register) and err (bit 2 of the status register) occur, the host controller will be expected to discard the bytes that it has already read from the receiver, which are associated with the unfinished frame. it must then wait for the next frame flag (rxfrmf) in order to continue. any unread contents of the rx data buffer are automatically discarded and no further rxf interrupts will be generated until the next frame flag (rxfrmf) interrupt occurs. 5. as the device can buffer up to 4 reed-solomon blocks i.e. 4 x 47 x 6 = 1128 bits = 141 bytes, in addition to the reed-solomon block it is currently decoding, it may be more convenient for the host controller to
cdpd mac and data pump processor page 19 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. use blkrdyf and blkrdym (bit 7 of the irq mask 2 register and bit 7 of the irq flags 2 register) as a form of counter, such that after 1, 2, 3, or 4 "block ready" interrupts, the host controller empties the receive buffer in one go. since, in this case, there is no way of knowing when the buffer is empty, an external timeout or byte counter is also required. 6. there is no buffer full indication, so if the rx data buffer register is not sufficiently empty when the fifth block has been processed, the latest received data (i.e. the fourth block) will be overwritten by the just completed fifth block. 5.1.4 transmit the host controller then processes the frames and decides upon a reply. gaining access and replying on the reverse channel can be done as follows: 1. before starting a transmission the colorf flag (bit 3 of the irq flags register) should be checked to have been set to ?1? to ensure the correct color code is used on the reverse channel (this could be done while also reading the status register during receive). 2. the idlef flag (bit 5 of the irq flags register) and the idle bit (bit 5 of the status register) should be checked to see if the forward channel is free. if the idle bit is ?1? the channel is free, if it is ?0? then there is communication with another system and the host controller will enter the defer state according to the cdpd specification (release 1.1, part 402, sections 5.3.3.1 and 5.3.3.2). 3. with the idle bit confirming a free channel, set the desired mod1 and mod2 output gains in the tx modem control register, then write ?1? to txrfm (irq mask 2 register, bit 3) and write "1" to enabtx (tx control register, bit 0). this will take the tx processing circuits out of powersave, so that blocks of data can then be loaded. 4. up to 4 reed-solomon blocks (i.e. 4 x 47 x 6 = 1128 bits = 141 bytes of data) can be loaded contiguously on a byte-by-byte basis. before any further data is loaded, the transmission must be started. this is done by writing ?1? to start (bit 1 of the tx control register), to indicate the start of data, i.e. the dotting sequence, reverse synchronization color code (from the forward channel) and the first frame byte will automatically be sent before the data in the buffer is despatched. 5. write the data into the tx data buffer register a byte at a time, using the irqn pin and the handshaking of the txf flag (bit 4 of the irq flags register). txf set to "1" indicates that another byte can be loaded into the tx data buffer register. when txf remains at "0", the buffer is full. 6. at each frame boundary write a ?1? to endfrm (bit 2 of the tx control register). 7. at the end of the transmission sequence, write ?1? to endseq (bit 3 of the tx control register). this will fill up the last reed-solomon block with ?1?s and send it with the continuity indicator set to ?0? (see the cdpd specification: release 1.1, part 402, section 4.6.4). 8. the tx buffer can be kept full and serviced with an interrupt routine. there is no buffer empty indication and failure to provide data after writing the start bit will cause the device to send undefined data. transmission of data does not begin until one complete block has been loaded into the tx buffer. 9. the transmission will automatically start within 8 bit-times of the last bit of an idle flag (see the cdpd specification: release 1.1, part 402, section 5.3.1). approximately two bit-times (104s) before the transmission is present at the txop1 and txop2 pins, the txrfen pin will be set to "1" and the txrfen bit (status register bit 3) will also be set to "1". the interrupt flag txrff (bit 3 of the irq flags 2 register) will also be set to "1" and an interrupt (irqn) will be generated if the mask has previously been enabled (txrfm, bit 3 of the irq mask 2 register set to "1"). 10. completion of the last reed-solomon block transmission will cause the txrfen pin to be reset to "0" and the txrfen bit (status register bit 3) will also be reset to "0". the interrupt flag txrff (bit 3 of the irq flags 2 register) will be set to "1" and an interrupt (irqn) will be generated if the mask has previously been enabled (txrfm, bit 3 of the irq mask 2 register set to "1"). finally, the outputs txop1 and txop2 will go to v bias . enabtx (bit 0 of the tx control register) should then be reset to "0", if required. 11. decf (bit 6 of the irq flags register) and dec (bit 6 of the status register) should be monitored to determine whether the m-es reverse channel transmitted data has been decoded correctly by the mdbs.
cdpd mac and data pump processor page 20 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 6. performance specification 6.1 electrical performance 6.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (v dd - v ss ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current into or out of v dd and v ss pins -30 +30 ma current into or out of any other pin -20 +20 ma e1 package total allowable power dissipation at t amb = 25c 400 mw derating above 25c 5.3 mw/c above 25c storage temperature -55 +125 c operating temperature -40 +85 c 6.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max. units supply (v dd - v ss ) 2.7 5.5 v operating temperature -40 +85 c xtal frequency 4.9149 4.9155 mhz
cdpd mac and data pump processor page 21 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 6.1.3 operating characteristics details in this section represent design target values and are not currently guaranteed. for the following conditions unless otherwise specified: xtal frequency = 4.9152mhz, bit rate = 19.2k bits/sec, noise bandwidth = bit rate, v dd = 3.0v to 5.5v, t amb = - 40c to +85c and v dd = 2.7v at t amb = 25c. notes min. typ. max. units dc parameters i dd (zero-power) at v dd = 3.0v 1 ? 1.0 10.0 a i dd (zero-power) at v dd = 5.0v 1 ? 1.0 10.0 a i dd (rx only) at v dd = 3.0v 1 ? 2.0 tbd ma i dd (rx only) at v dd = 5.0v 1 ? 4.0 tbd ma i dd (tx only) at v dd = 3.0v 1 ? 2.0 tbd ma i dd (tx only) at v dd = 5.0v 1 ? 4.0 tbd ma i dd (rx and tx) at v dd = 3.0v 1 ? 3.5 tbd ma i dd (rx and tx) at v dd = 5.0v 1 ? 7.0 tbd ma ac parameters tx output tx o/p impedance (powersaved) 2 300 500 ? k ? tx o/p impedance (operating) 2 ? 1.0 2.5 k ? signal level 7 0.9 1.0 1.1 v p-p txf latency 10 tbd 16 tbd s tx processing delay 9 ? 1 ? bit txop1 or txop2 dc level (transmitting "1010...") tbd 50% tbd v dd (in tx mode, mod1 and mod2 gain off) tbd 50% tbd v dd (in powersave - tx mode disabled) tbd 50% tbd v dd (in zero-power mode) ? 0 ? v rx input rx i/p pin impedance (at 100hz) 10 ? ? m ? rx i/p amp open loop voltage gain (i/p = 1mv rms at 100hz) ? 500 ? v/v input signal level 8 0.7 1.0 1.3 v p-p rxf latency 10 tbd 16 tbd s rx processing delay 9 ? 7 ? bits xtal/clock input 'high' pulse width 3 40 ? ? ns 'low' pulse width 3 40 ? ? ns input impedance (at 100hz) 10 ? ? m ? gain (i/p = 1mv rms at 1khz) 20 ? ? db c interface input logic "1" level 4, 5 80% ? ? v dd input logic "0" level 4, 5 ? ? 20% v dd input leakage current (v in = 0 to v dd ) 4, 5 5.0 ? +5.0 a input capacitance 4, 5 ? 7.5 ? pf output logic "1" level (l oh = 120a) 5 90% ? ? v dd output logic "0" level (l ol = 360a) 5, 6 ? ? 10% v dd 'off' state leakage current (v out = v dd ) 6 ? ? 10 a
cdpd mac and data pump processor page 22 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. operating characteristics notes: 1. not including any current drawn from the device pins by external circuitry 2. small signal impedance 3. timing for an external input to the clock/xtal pin 4. wrn, rdn, csn, a0 ? a2 pins 5. d0 - d7 pins 6. irqn pin 7. measured at txop1 and txop2 with mod1/2 gain blocks set to 0db 8. measured at rxfb pin 9. bit period = 52s 10. from the availability of the last bit in a block. this implies that the first bit in the same block will be delayed by typically 22ms. 6.1.4 timing diagrams for the following conditions unless otherwise specified: xtal frequency = 4.9152mhz, v dd = 3.0v to 5.5v, t amb = - 40c to +85c and v dd = 2.7v at t amb = 25c. notes min. typ. max. units c parallel interface timings (ref. figure 5) t acsl address valid to csn low time 0 ? ? ns t ah address hold time 0 ? ? ns t csh csn hold time 0 ? ? ns t cshi csn high time 1 6 ? ? clock cycles t csrwl csn to wrn or rdn low time 0 ? ? ns t dhr read data hold time 0 ? ? ns t dhw write data hold time 0 ? ? ns t dsw write data setup time 15 ? ? ns t rhcsl rdn high to csn low time (write) 0 ? ? ns t racl read access time from csn low 2 ? ? 30 ns t rarl read access time from rdn low 2 ? ? 25 ns t rl rdn low time 35 ? ? ns t rx rdn high to d0-d7 3-state time ? ? 10 ns t whcsl wrn high to csn low time (read) 0 ? ? ns t wl wrn low time 35 ? ? ns notes: 1. xtal/clock cycles at the xtal/clock pin 2. with 30pf max to vss on d0 - d7 pins
cdpd mac and data pump processor page 23 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. figure 5: controller parallel interface timings
cdpd mac and data pump processor page 24 of 24 CMX989 advance information 2001 mx-com, inc www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480231.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 6.2 packaging figure 6: 28-pin tssop mechanical outline: order as part no. CMX989e1

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